DCS seminar talk: Thomas Wenisch

Today there is a talk by Thomas Wenisch from the Department of Electrical and Computer Engineering at Carnegie Mellon University, which is on Temporal Memory Streaming. This is a systems talk. Abstract for the talk is below:

While semiconductor scaling has steadily improved processor performance, scaling trends in memory technology have favored improving density over access latency. Because of this processor/memory performance gap­ often called the memory wall­ modern server processors spend over half of execution time stalled on long-latency memory
accesses. To improve average memory response time for existing software, architects must design mechanisms that issue memory requests earlier and with greater parallelism. Commercial server applications present a particular challenge for
memory system design because their large footprints, complex access patterns, and frequent chains of dependent misses are not amenable to existing approaches for hiding memory latency. Despite their complexity, these applications nonetheless execute repetitive code sequences, which give rise to recurring access sequences ­a
phenomenon I call temporal correlation. In this talk, I present Temporal Memory Streaming, a memory system design paradigm where hardware mechanisms observe repetitive access sequences at runtime and use recorded sequences to stream data from memory in parallel and in advance of explicit requests.

I think this work is interesting in that it takes advantage of past accesses in order to predict future accesses and do prefetching. It is trying to do some intelligent mechanism for improving performance of applications, by using statistical sampling and distributions. Main memory accesses cost 100s of cycles. The key idea is recording and replaying recurring miss sequences with temporal memory streaming. There is a paradigm shift in computer architecture from clock and instruction level parallelism (ECE728 dejavu from University of Waterloo's undergrad Computer Engineering program). His future work is dealing with architecture support for programmability for parallel software.

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